In recent years, high speed semiconductor devices have been causing problems such as power supply noise, signal reflection, inter-signal interference (crosstalk) and EMI (Electromagnetic Interference). Conventionally, a power supply system and a signal system were independently discussed, analyzed and designed, such as power supply noise and EMI, degradation of signal quality due to signal reflection and skew which also causing EMI, degradation of a signal waveform due to inter-signal interference and/or EMI, so on.
However, in these several years, as a signal density and a signal transmission rate increase, direct interaction between signals and power supplies has been pointed out, which occurs during signal transmission inside the semiconductor device packages or printed circuit boards. Such a problem is described in Non-Patent Literature 1 and Non-Patent Literature 2.
Here, direct common mode noise transition from a power supply line to a signal line, or oppositely, direct noise transfer from a signal line to a power supply line during signal transmission due to a propagating signal and so on are causing new problems. These direct signal-power interactions cause EMI which results in an operation instability to the Gbps-clalss high-speed devices by generating a positive feed back loop between signal and power delivery systems.
Generally, it is proposed to provide a ground shield in order to prevent inter-signal interference, including noise. However, in a case that a part of signal line is a bonding wire, it is difficult to provide a ground shield surrounding each of all the bonding wires in the semiconductor device. Not only difficulty in manufacture such a semiconductor device, the semiconductor device becomes large in size, thus, the manufacturing cost increases. Therefore, it is preferable to achieve electrical performance without need for a special high-cost manufacturing process.
FIGS. 1A and 1B compare the output signal spectra from exactly the same LSIs mounted on the two different types of interposer. FIG. 1A is a graph showing a case where an interposer has bonding wires. FIG. 1B is a graph showing a case where an interposer is of a flip-chip type. In the flip-chip type interposer, a power supply line and a signal line are provided in different layers and are shielded from each other by a ground plane.
These two LSIs operate in the signal rate of 6.4 Gbps. These output signal spectra were obtained by performing Fourier transformation on the observed common mode signal waveforms. In these graphs, the horizontal axis shows frequency and the vertical axis shows intensity of noise. The solid line indicates a case where only a signal was inputted to the interposer with no power supply noise, and the broken line indicates a case where the signal was inputted to the interposer with power supply noise.
The following facts are observed from FIGS. 1A and 1B. That is, in a case of the flip-chip type interposer, because the signal and the power supply are well shielded, the common mode noise spectrum is well coincident regardless of existence or non-existence of the power supply noise. On the other hand, in a case of the interposer which contains bonding wires, the difference of the common mode noise between the existence and non-existence of the power supply noise is very large, especially in a mega-hertz region. The reason for this large difference in the mega-hertz region is that a main frequency component of the power supply noise is in the mega-hertz region in this example. The flip-chip type interposer is more expensive than the interposer having bonding wires.
As shown in the above example, direct noise transition from the power supply system to the signal system in the interposer is large when the semiconductor device has bonding wires therein, thus some measure is necessary which reduces the noise transition or interference. That is, for the next generation low-cost and high-speed devices, a new scheme is required that reduces interference and coupling between the power supply and the signal as well as reducing power supply noise itself. In addition, as suggested by the various publications, for stable operations of the giga-bps-class high-speed devices, it is also necessary to reduce inter-signal interference (crosstalk) and signal reflection caused by impedance discontinuity. Because the layout resource on the interposer is limited especially for the low-cost interposer, it is ideal to satisfy all the requirements with optimum balance.
FIGS. 2A to 2C show an example of the arrangement of bonding wires which connect an LSI chip to an interposer substrate, described in Patent Literature 1 (U.S. Pat. No. 6,538,336). FIG. 2A is a perspective view showing the arrangement of the bonding wires. FIG. 2B is a side view showing the arrangement of the bonding wires. FIG. 2C is a sectional view of the bonding wires along the line A-A′ in FIG. 2B.
As seen from FIGS. 2A and 2B, the LSI chip is mounted on the interposer substrate in this example. Bonding pads are arranged in two lines in each of the surface of the LSI chip and the surface of the interposer substrate. The bonding wire is connected from the bonding pad on the LSI chip to the bonding pad on the interposer substrate.
The symbols of “S”, “G” and “P” shown in FIG. 2C mean that the bonding wires are for a signal, ground and power supply, respectively. As seen in FIG. 2C, the ground bonding wire or the power supply bonding wire is arranged in adjacent to the signal bonding wire. Here, a pre-determined voltage may be applied to the ground bonding wire and the power supply bonding wire in which the pre-determined voltage may be replaced with a very low frequency signal compared to that of the signal bonding wire. From this point, the bonding wires for ground, power supply and the extremely low frequency signal are, in short, referred as fixed voltage bonding wires.
As seen from FIG. 2B, the bonding wire connected with one of the bonding pads of a second one of two lines which is arranged on the LSI chip on the side near the mounting substrate, is provided lower than a bonding wire connected with one of the bonding pads of a first line as the other line. In other words, the bonding wires connected with the first line of bonding pads are contained in a first envelope, and the bonding wires connected with the second line of bonding pads are contained in a second envelope, which is located below the first envelope.
In this way, in the example of FIGS. 2A to 2C, the high-speed signal bonding wires and the fixed voltage bonding wires are alternately arranged in two lines. In this case, the high-speed signal bonding wires are shielded by the fixed voltage bonding wire. As a result, crosstalk between the high-speed signals is restrained.
To arrange the bonding wires as mentioned above, basically, it is necessary to arrange the high-speed signal bonding pad and the power supply bonding pad or the ground bonding pad alternately in line on the LSI chip or the interposer substrate.
FIG. 3 is a plan view showing another example of the arrangement of bonding wires which connect the LSI chip and the interposer substrate, as shown in the Patent Literature 1. In the example of FIG. 3, bonding pads on the LSI chip are arranged in two lines in which one is shifted from another.
The crosstalk between the high-speed signal bonding wires can be reduced by using the bonding pads arranged in two lines and handling the high-speed signal, and the power supply, the ground and/or an extremely low frequency signal in the same manner. According to this technique, although the number of bonding pads for an I/O circuit tend to increase, a sufficiently good crosstalk restraint effect is attained depending on the ratio of the high-speed signal bonding pads and the fixed voltage bonding pad.